gEDA-dev: Thoughts on buses in gschem

[Peter TB Brett]

Hi folks,

I want to share with you some (still rather sketchy) thoughts I've had 
on a better behaviour for buses in gschem. At the moment, buses in 
gschem are more or less graphical -- that is, in most examples of bus 
use, the buses could be quite happily omitted.  This e-mail is to 
explain how I think they could work usefully (for instance, it allows 
heirachical buses).

(1) Make '[' and ']' special characters in netname attributes and 
pinlabel attributes.

(2) Make the netname attribute of a bus a bit like an range in VHDL.  
Example: "netname=MEMDATA[7:0]".  In this case, the bus expands out into 
8 nets: MEMDATA7, MEMDATA6, MEMDATA5 ... MEMDATA0 *in that order*.  
"netname=MEMDATA[0:7]" would expand in the opposite order (the 
distinction between 'to' and 'downto' in VHDL).  After expansion, those 
nets behave exactly like normal nets for the purpose of netlisting (as 
if the nets had been stacked on top of each other on the schematic).  A 
bus netname attribute without exactly one square bracket/colon 
expression generates a netlisting error.

(3) Add a new "bus pin" atom. This would have attributes pinseq (a 
single number), pinlabel (a string similar to a bus's netname), 
pinnumber (a comma-separated list of pin numbers in the same order as 
the pinlabel expands), and pintype (a single pintype value). Example:

  pinseq=2
  pinlabel=DIN[0:7]
  pinnumber=4,3,2,1,13,14,15,16
  pintype=in

A bus pin pinlabel attribute without exactly one square bracket/colon 
expression generates a netlisting error.

(4) For slotted components, a slotdef where a bus pin must be specified 
would have a comma-separated sublist of pins enclosed in parentheses. 
Example: "slotdef=3:4,5,(6,7,10,11),8", where the pin with pinseq=3 is a 
4-way bus pin.

(5) Connecting a bus to a normal pin or a normal net to a bus generates 
a fatal error when netlisting.

(5) Netlisting process: when a bus is connected to a bus pin, the 
netname and pinlabel attributes are expanded in the correct order, and 
are connected in pairs until the end of one of the ranges.  If the 
ranges have different lengths, it generates a warning when netlisting, 
and a DRC warning too.  Example: there is a bus with "netname=D[5:2]" 
and a symbol with a bus pin "pinlabel=IN[0:4]".  The nets would be 
connected as follows:

  D5 - IN0
  D4 - IN1
  D3 - IN2
  D2 - IN3

IN4 would be NC, and a warning would be generated.

(6) Netlisting process: when a symbol representing a subcircuit in a 
heirachical schematic has a bus pin, the bus is expanded and then 
connected to nets in the subcircuit just like normal nets, and just like 
normal nets, bus elements that have no corresponding subcircuit generate 
a warning.

Any comments/suggestions/implementations gratefully received.

Peter