gEDA-dev: Verilog Obfuscator

[John Sheahan]

Tim Freedom wrote:
> Beyond 'vo' [1] which is a free tool (not open sourced so can't modify,
> enhance, fix, tweak, etc) are there any other alternatives out there ?
> 
> Has anyone spent the time to code-up a perl script to do the job that
> they're willing to share with the community ?

testbench, RTL or gate?
Hierarchical as well as flat?
supporting references into distant modules?

I wrote something for mangling vcd  names (vcd_mangle) once, was 
trivial. Gate would not be particularly difficult, particularly
flattened gates. (which might suffice for vendor test cases, for example)
The role for a testbench mangler is not clear to me.

john