gEDA-dev: some suggestions

[Peter TB Brett]

On Thursday 14 December 2006 21:19, Stuart Brorson wrote:

> I'll bet you don't use any busses, and your netnames are all global.

I don't use hierarchical buses.  My netnames aren't all global.  I've never 
found any reason for them to be...  I just put VCC and GND pins on my 
hierarchical symbols.  I didn't even know you could have global netnames.  
Can you?

> Hierarchical busses remain a problem for gEDA.  That is, I can't just
> connect a bus called foo[7:0] to a pin on a block, and have all the
> nets in foo[7:0] show up at the lower level.  Pins are strictly
> single-net constructions as gEDA currently stands.

I agree.  Bus pins are something I've wanted for a while (and in particular 
yesterday), and I made a detailed suggestion as to how they could be most 
easily implemented in gEDA in my e-mail with message ID 
<44B4D860.30401 at peter-b.co.uk>.  After some discussion about all the very 
complicated things that people wanted buses to do that my proposal didn't (on 
account of the fact it was a very simple first-pass approach), nothing was 
done about it.

> As for other types of hierarchy, a big problem arises if you have one
> top-level block, and in it you want to instantiate multiple identical
> copies of a lower-level block.  This is common in IC design, but I
> have also done such a thing in a 4 port IO PCB I did once.  Each
> lower-level block is identical, but must have different refdeses and
> different netnames on the lower level so that the different nets
> aren't all shorted out in the resulting netlist.  Acceptable netnames
> can be of the type foo1_upper:bar_lower, foo2_upper:bar_lower, etc.
> Acceptable refdeses might be U1:U5, U2:U5 and so on [1].  Doing this
> is a problem for both gschem and for gnetlist.
>
> Unless things have changed in the last few months, gEDA can't handle
> these issues.  If I'm wrong, please tell me!

Things have changed.  My PCB has 8 identical input stages on it, and each one 
has its own R1, R2, C1, C2 etc.  gnetlist turns these into refdeses of the 
form A1/R1 and so on and so forth.

>
> [1]  Then these refdeses are changed at layout time to something more
> sensible like U5, U6, etc, and backannoed into the schematic.
> (Good -- actually any -- backanno is the other important missing piece
> in gEDA.)  Doing this in a hierarchical design in not trivial, and is
> prone to error. ViewLogic does something they call OATS, which is some
> scheme to overwrite lower-level refdeses from the top level.  It
> always broke for me, but I probably didn't understand it.
>

During my gap year I head __64__ (yes, count 'em) line driver subcircuits on a 
PCB I designed (a contractor did the layout).  The hierarchy worked nicely, 
but I had to write a program to munge 'flatten' the hierarchical refdeses (it 
also generated my BOM).  Obviously this is tricky to do 'nicely' when there's 
one system being used for schematic capture and another for layout.

Peter


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