gEDA-dev: Icarus Verilog snapshot 20060809

Stephen Williams steve at icarus.com
Wed Aug 9 21:53:26 EDT 2006


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Hello, testers!

It's time again for an Icarus Verilog snapshot. I've cleared a bunch
of bug reports and added some new features. Including one feature
above and beyond the call of the Standard: % or real values:-)
Anyhow, it's ready for a fresh batch of bug reports, so here goes.

<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20060809.tar.gz>
<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20060809.txt>


* Release Notes for Snapshot 20060809

Some handling of real values is improved. Real valued literals are
handled in net contexts (continuous assignment, etc.). Also, modulus
of real operands now works. (This is an extension to the Verilog
standard.)

The power operator (**) now works.

Signed right shift works properly now.

The $sscanf and $fscanf are introduced, and work at least for basic
numeric values.

The release function now works to undo general force statements, and
not just contant force statements.

Delay constants up to 64 bits are supported. This at first doesn't
seem like an issue, but when precisions are mixed, it becomes
surprisingly easy to overflow 32bit delays.

The driver is reworked to pass many preprocessor details through a
temporary file instead of on the command line of a system(3)
call. This prevents confusing and incorrect shell processing of
complex strings passed as values to -D flags.

Various other little fixes.


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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