gEDA-dev: Re: Icarus Verilog for post synthesis simulation

[John Sheahan]

Stephan Boettcher wrote:

>> I don't normally bother with back-annotated timing data and never
>> feel the need.
> 
> Why?

probably because its an FPGA. If the vendor static timing says it works, 
it probably does. RTL simulation is so much faster and gives you 99+% of 
the benefit.

But for an asic, with those mask costs, full timing back annotated
simulation does give that bit of extra confidence on those cross clock
domain paths that STA does not handle well.

Its so much more embarassing to get masks wrong.
john