gEDA-bug: [ geda-Bugs-1741910 ] various issues with busses in Verilog back end

[SourceForge.net]

Bugs item #1741910, was opened at 2007-06-22 16:01
Message generated for change (Tracker Item Submitted) made by Item Submitter
You can respond by visiting: 
https://sourceforge.net/tracker/?func=detail&atid=818426&aid=1741910&group_id=161080

Please note that this message will contain a full copy of the comment thread,
including the initial issue submission, for this request,
not just the latest update.
Category: None
Group: None
Status: Open
Resolution: None
Priority: 5
Private: No
Submitted By: Jeff Trull (jetrull)
Assigned to: Nobody/Anonymous (nobody)
Summary: various issues with busses in Verilog back end

Initial Comment:
I know of three problems with the Verilog back end related to bussed wires and I/Os:

1) bussed outputs appear in the port listing twice: once as inputs, once as outputs
2) single-bit busses whose only bit is 0 appear as scalars without an index in the port list
3) instance names with square brackets are not escaped

An example schematic is attached.

Regards,
Jeff Trull


----------------------------------------------------------------------

You can respond by visiting: 
https://sourceforge.net/tracker/?func=detail&atid=818426&aid=1741910&group_id=161080