gEDA-announce: Icarus Verilog Snapshot 20060124

[Stephen Williams]

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To prove that I'm still alive, I'm making a new snapshot of
Icarus Verilog:

<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20060124.tar.gz>
<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20060124.txt>

In fact, I have been pretty busy with other things, but there are
some real improvements here that warrant a release.

Release Notes for Icarus Verilog Snapshot 20060124

A few new features have been added to allow proper simulation with
newer Xilinx UNISIM models. (They are starting to use Verilog 2001
features.) And also various bug fixes in this release.


- - Primitive and continuous assign delays can now be non-constant. This
  needed some new run-time support, so vvp had a slight format change,
  and certain new optimizations follow as a result.

- - Bug handling certain constant sub-expressions in concatenation
  expressions. Also, allow concat expressions in constant contexts.

- - Support for wide divide expressions.

- - Fixes for stubborn compilers.

- - Fix bugs in padding of signed expressions.

- - More fixes for following the data types of expressions.

NOTE: The tgt-fpga code generator does not compile.


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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