gEDA-announce: [ANNOUNCE] MyHDL 0.5 released

[Jan Decaluwe]

Hi all:

I'm pleased to announce the release of MyHDL 0.5.

MyHDL is an open-source package for using Python as a hardware
description and verification language. Moreover, it can convert
a design to Verilog. Thus, MyHDL provides a complete path
from Python to silicon.

MyHDL 0.5 has many new features, in particular with regard to
conversion to Verilog. The converter automates certain tasks
that are hard in Verilog directly.

For a complete overview, go here:
   http://myhdl.jandecaluwe.com/doku.php/overview

The manual is here:
   http://www.jandecaluwe.com/Tools/MyHDL/manual/MyHDL.html

To find out the details of what's new, go here:
   http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5

You can download the release from SourceForge:
   http://sourceforge.net/project/showfiles.php?group_id=91207

Best regards,

Jan Decaluwe

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com