Hi folks, Slightly off-topic, but I need some suggestions: I'm currently building an ADC board to go with an existing microprocessor board I have available. It's going to have eight 100 kHz 12-bit serial ADCs. Now, the problem I have is that I want to read from all eight channels simultaneously and at regular intervals, but I have no control over how often or regularly the microprocessor will request data. I've written a snippet of VHDL which I could load into a small CPLD to turn the serial data into a stream of parallel data, but I need to have a decent size buffer, and affordable configurable logic devices don't have any RAM worth speaking of and too few registers to implement a memory controller + buffer manager. So to cut a long story short, I've more-or-less decided on using a CPLD for deserializing the ADC data, with a high-end 16-bit PIC for buffering/talking to the main microprocessor system. Does that make sense? Am I missing an obvious and somewhat simpler solution? Also... can anyone suggest a good way to build a square-wave clock generator that can vary from 4kHz to 4MHz with a minimum of fuss and a decent mark-space ratio? I've been scratching my head about this for a couple of days, and I still don't have a decent solution... Cheers, Peter -- Fisher Society committee http://tinyurl.com/o39w2 CUSBC novices, match and league secretary http://tinyurl.com/mwrc9 CU Spaceflight http://tinyurl.com/ognu2 v3sw6YChw7$ln3pr6$ck3ma8u7+Lw3+2m0l7Ci6e4+8t4Gb8en6g6Pa2Xs5Mr4p4 hackerkey.com peter-b.co.uk
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