John Griessen wrote:
1) Assign unique "refdes" value to all netlistable logical symbols in the schematic. If the logical symbol is one of several in a "PHYSICAL_package", then assgined "refdes" to each logical symbol such as "Uxx_yy"; where yy is the value to identify a particular "LOGICAL_SYMBOL" among several within a "PCB_PACKAGE"; and xx value is the ID to differentiate among all "PCB_PACKAGE" for your design. Uxx is what you want tosee in your PCB netlist.
maybe I misunderstand something here, but if you want to say'_' in Uxx_yy is actually a separator you should come up with a positive definition
of what a standard refdes can be made of.The sloopy way chars get assigned special meanings with all sorts of identifiers
in geda really annoys me - and imho bites everyone in the long run. The above example would make another step to:"you may not use ':' in blah, unless foo is set to 5, and '-' can bit you in some circumstances. I can assure you that '_' is valid in refdes, unless it's used for a bus in which case... Depending on the phase of the moon, '/' in an identifier can mean either:..."
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