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gEDA: icarusVerilog - VVP assembly instructions.
- To: geda-dev@xxxxxxxx
- Subject: gEDA: icarusVerilog - VVP assembly instructions.
- From: Karthik Parashar <karthik_n_parashar@xxxxxxxxx>
- Date: Thu, 16 Mar 2006 11:02:41 -0800 (PST)
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Hi Steve,
One more question regarding the vvp assembly.
I saw a #define MAX_VEC (256*1024) and an assert on
this.
I guess this has something to do with the 64K bit wise
registers in a vvp-thread.
I could have expected this to be 2 times 2^16 because
of 2 bits per signal to denote X and Z values.
However, this is 4 times 2^16.
Please explain the MAX_VEC definition here.
Regards,
~Karthik.
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