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gEDA: Iverilog : problem with $setuphold on bus signal

Hi Steve and all,

I tried on 2 different versions (0.8 & 20060409) and found the following problem.
Both failed to compile.


==================================================

wire D_7 = D[7];


...


// fail
$setuphold(posedge TCK &&& XMG, negedge DIN[7], 0, 0,
notifierX24,,,TCK_X, D[7]); // fail

// pass
$setuphold(posedge TCK &&& XMG, negedge DIN[7], 0, 0,
notifierX24,,,TCK_X, D_7); // pass

==================================================




Thanks a lot for your help.

Best regards,
Steven.