Re: gEDA: iverilog non-descriptive error

[Stephen Williams <steve@xxxxxxxxxx>]

> -------------------------8<-------------------------
> iverilog -tfpga -osimple.edif simple.v
> simple.v:8: warning: Process not synthesized.
> fpga target: unsynthesized behavioral code
> -------------------------8<-------------------------
>
> simple.v is a perfectly valid small piece of code, which will compile 
> fine under other tools.  When looking at the EDIF output, nothing is 
> created but a hanging buffer, and all the outputs are left undriven.
>
> What is this warning telling me that I need to fix?
>
> Please reply to my email address, since I am not subscribed to the list.
> Thanks!

It's telling you that the initial or always statement on
line 8 in simble.v was not synthesized, probably because
the synthesizer part of Icarus Verilog cannot handle something
about it. Your code will simulate fine without the -tfpga,
since the compiler clearly knows how to elaborate the code.

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."