gEDA: Re: Icarus Verilog radmap

[Stephen Williams <steve@xxxxxxxxxx>]

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John McCaskill wrote:

> Do you have a road map of the features you will be adding to Icarus
> posted somewhere? We have started using more advanced features such as
> generate, SmartModels for Xilinx PPC and MGTs, and mixed Verilog and
> VHDL.  

Generate is high on my list.

SmartModels were top of my list, and I'd made some progress on
that front, to the point where I could *load* the PPC smart model.
Xilinx was interested in getting them working.

However, I couldn't get past some initial startup.

There is a PLI-1-to-smartmodel adapter that I loaded using the
cadpli module, and that in turn loads the SmartModel. But I got
stumped by its behavior, and couldn't get far.

To implement SmartModel support, I really will need support from
the vendor, Synopsis I believe, and/or from model writers. I got
support from places within Xilinx, but there was only so much we
could do.
- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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iD8DBQFD4+rprPt1Sc2b3ikRAv9vAJ0aZlNes+USiwh2u0dOsHW5GoszegCfeWhX
lEbHoZFG9X+Z/gsxd0U8yHM=
=jsD5
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