Re: gEDA: Verilogrelative include path handling

[Larry Doolittle <ldoolitt@xxxxxxxxxxxxxxx>]

On Fri, Feb 03, 2006 at 04:19:52PM -0600, John McCaskill wrote:
> Do you have a road map of the features you will be adding to Icarus
> posted somewhere? We have started using more advanced features such as
> generate,

generate ... Generate ... GENERATE !!!!

> SmartModels for Xilinx PPC and MGTs,

What are those?

> and mixed Verilog and VHDL.  

Ain't gonna happen.  Convert your VHDL to Verilog with vhd2vl,
then you can mix the designs.  The VHDL synthesis subset where
that toolchain works OK is broad enough that at least one person
has learned to stay within it for real designs.

      - Larry