gEDA: Verilogrelative include path handling

[Stephen Williams <steve@xxxxxxxxxx>]

This bug report:

https://sourceforge.net/tracker/index.php?func=detail&aid=1412755&group_id=149850&atid=775997

Points out an issue with include files that has goon unnoticed by
me for a while. I've got 2 patches now to change the search behavior
for include files with relative paths, but I would like to get a
reading of what the rest of the world does before commiting.

The example:

hdl/a.v:
`include "b.v"

hdl/b.v:
// some verilog code

shell prompt:
iverilog  hdl/a.v

hdl/a.v:1348221540: Include file b.v not found

So I take it this should work? What do other tools do here? I'm
inclined to apply a patch, but I just want to double-check with
other tools.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."