Re: gEDA-dev: [pcb] thin lines for assembly layer?

[Dan McMahill <dan@xxxxxxxxxxxx>]

DJ Delorie wrote:
> For one of my recent footprints, I added an 0.01 mil silk where the
> physical part was, so I could verify the pads and such.  It got me to
> thinking, maybe we could special-case "thin" silk to be used for the
> assembly drawing?  I.e. if silk is <0.1mil, it's not drawn on the
> regular silk print, but is drawn on the assembly print.  For the GUI,
> it's drawn just like it is now.
>
> I'd rather have a special layer just for assembly, but that means
> adding to the Element file format and major changes to pcb to support
> it all.  The thin-silk change is a hack, but a small hack and no file
> format changes are required.
>
> Thoughts?  Should we wait until the hard "more layer types" change is
> made, or add the hack now?

Even though I'd generally rather not do such hacks, having very think 
silk on the screen that doesn't go into the silk gerber file could be 
most useful right now.  I don't think I have a problem with it.  Maybe 
the biggest issue is how to handle DRC.  Right now DRC will complain 
loudly.  We could easily make it not complain about <0.1 mil silk but 
then it might not catch a real mistake.

How much work do you think it really would be to allow ElementLine and 
ElementArc to have a flag which specifies a layer and to support 
multiple annotation layers this way?

-Dan


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