RE: gEDA-dev: [pcb] thin lines for assembly layer?

["Timmerman, Bert" <bert.timmerman@xxxxxxxxxxxxxx>]

HI DJ, Peter, and all,

Maybe it's an option to add a "NOPLOT" flag (0x1****** ... or some other
value ) to this thin line of 0.01 mil, as to not plot it in the gerber
files for front/back silk etc.

This flag could be used for other stuff as well.

This wouldn't break the file format and could easily be implemented,
that is, if there a spare bit "left over" in the flag byte.

This placement courtyard could be used for DRC as well (overlapping
landpatterns).

Just my EUR 0.01

Kind regards,

Bert Timmerman.

-----Original Message-----
From: geda-dev-bounces@xxxxxxxxxxxxxx
[mailto:geda-dev-bounces@xxxxxxxxxxxxxx] On Behalf Of DJ Delorie
Sent: Wednesday, August 09, 2006 8:05 AM
To: geda-dev@xxxxxxxxxxxxxx
Subject: Re: gEDA-dev: [pcb] thin lines for assembly layer?


> Wait.  One of the most common requests I hear from Cambridge users
> is for a mechanical layer in PCB.

I don't think it's just you folks.

> Even if it does require major backwards-compatibility breakage, I
> think that it's worth doing as soon as you guys can find the time to
> do it.

Or as soon as you guys can :-)


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