gEDA-dev: Re: Icarus Verilog for post synthesis simulation

[Stephen Williams <steve@xxxxxxxxxx>]

Evan Lavelle wrote:
> Stephen Williams wrote:
> 
>> Agreed. That is the right way to deal with it. SDF really has
>> two parts. The parser that reads the SDF files can be written
>> as a system task, and iSDF is done that way. But there needs to
>> be some specific specify related infrastructure in the vvp run-
>> time to provide the needed features. iSDF used some patched in
>> hacks to get by, but we really need the core from specify block
>> support for a proper job.
> 
> And $setuphold/etc.?

It'd be nice to support all those things in the long run, but
first step would be to support basic timing paths  and work up
to that. I believe there is nothing in the devel branch vvp that
would preclude these sorts of timing checks.

Getting SDF working would involve first getting some specify block
support in place.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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