Re: gEDA-dev: Re: Icarus Verilog for post synthesis simulation

[Evan Lavelle <eml-geda@xxxxxxxxxxx>]

Stephen Williams wrote:

> Not that I'm dismissing SDF at all. No sir, there are certainly
> latent requests for SDF support, but I am faced with my own
> day-to-day priorities. Filling in system tasks, and implementing
> generate statements are pretty high, not to mention performance.

I'm not suggesting that you put any work into timing support (I'm sure 
that this is a lot more difficult than it might seem at first sight), 
but I would say, in support of timing sims:

1 - STA is only as good as the constraints you put into it. On a complex 
device, it can be very difficult to make sure that you've constrained 
everything; you can easily get an STA pass for a chip that'll never 
work. This is as true of FPGAs as ASICs.

2 - There are only two ways to check that your constraints were valid: 
you can wade through dozens or hundreds of timing reports (*very* hard 
work), or you can run a back-annotated timing sim. If this is an ASIC 
and you're not doing the back-end work, then you may have trouble 
getting someone to actually generate all the reports you need. On the 
other hand, a single sdf file tells you everything; you just run the 
sims, and see if the chip passes. Also true of FPGAs.

3 - Sometimes a timing sim will tell you something that STA won't tell 
you. I had a case recently where a library PLL was "guaranteed by 
design", including the digital parts. The digital bits were false 
path'ed, and so missed STA. However, there was timing data in the sdf 
(don't ask how it got there - I don't know!), and the timing sim failed 
- the digital feedback divider didn't work. Turned out it wasn't 
"guaranteed by design".

4 - On the other hand, sdfs may not be accurate. On my last chip the 
vendor added a 15% derating in PrimeTime to cover path-based 
uncertainty, OCV, and so on, and they said that it wasn't possible to 
include this in the sdf data. They couldn't explain why. Anyway, the sdf 
was not as accurate as the STA results.

In short, I personally always run timing sims, on FPGA and ASIC. Of 
course, you can only test what you exercise with the testbench, but you 
can't beat it.

Evan


_______________________________________________
geda-dev mailing list
geda-dev@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev