gEDA-dev: Re: Icarus Verilog for post synthesis simulation

[Stephen Williams <steve@xxxxxxxxxx>]

Stephan Boettcher wrote:
> GÃnter Dannoritzer <dannoritzer-S0/GAf8tV78@xxxxxxxxxxxxxxxx> writes:
> 
>> I tried to compile iSDF 0.2.1 with the latest development snapshot of
>> Icarus (verilog-20060618) and it does not compile.
> 
> I am not surprised.
> 
> At that time, ivl was not looking at specify timing at all, so that
> iSDF needed to do a lot of dirty tricks to produce the delay paths to
> annotate.  Obviously, this was not going to survive a few years of
> development.
> 
> When ivl/vvp does support the specify delays, SDF annotation becomes a
> lot easier.  That is were I'd spend some time on, if I had any.

Agreed. That is the right way to deal with it. SDF really has
two parts. The parser that reads the SDF files can be written
as a system task, and iSDF is done that way. But there needs to
be some specific specify related infrastructure in the vvp run-
time to provide the needed features. iSDF used some patched in
hacks to get by, but we really need the core from specify block
support for a proper job.

I do find time to work on other things, but I need to give
priority to paying work first, so this task needs time or a
sponsor. (Or both:-)

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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