gEDA-dev: Re: Icarus Verilog for post synthesis simulation

[Stephen Williams <steve@xxxxxxxxxx>]

Stephan Boettcher wrote:
> Stephen Williams <steve-TQXSILARuq3QT0dZR+AlfA@xxxxxxxxxxxxxxxx> writes:

>> I also don't know the current status of the iSDF plugin.
> 
> I did not look into the vvp code for a long time. Since the structural
> concepts in there have evolved quite a bit, I assume there is a lot of
> work to do before iSDF can be made working.

... in the devel trunk, yes. The 0.8 branch may be a smaller leap,
although it would be most great if it were redone for the new devel.
There are new delay objects in the devel vvp that should make it
much easier... especially if Icarus Verilog starts paying attention
to the specify block contents.

>> I don't normally bother with back-annotated timing data and never
>> feel the need.
> 
> Why?

Because it's an FPGA, and if the vendor static timing says it
works, it probably does.(*) For that matter, where do you think
the "dynamic" timing information comes from in an FPGA?-)

Not that I'm dismissing SDF at all. No sir, there are certainly
latent requests for SDF support, but I am faced with my own
day-to-day priorities. Filling in system tasks, and implementing
generate statements are pretty high, not to mention performance.

* Thanks to John Sheahan for this well formed sentence.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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