gEDA: PCB and GAF PIN Swapping and Gate Swapping

[Stephen Meier <smeier@AlchemyResearch.com>]

I just want to get a few brainstorm ideas out on the table for discussion.

I am in the middle of a board layout which has almost one thousand nets 
with a 900 pin PLD. This design is using a customized version of GAF 
which allows me to use hierical buses. It is a very rough version and I 
have given Ales a copy of the code with the modifications. After I get 
this board out the door I expect to work on cleaning up the 
customizations for possible future inclussion in GAF.

Durring the layout process I find myself moving back and forth between 
gschem, gnetlist and pcb rearanging how the io pins of the PLD are used. 
For the pld a xilinx sparten 3 I have created a number of symbols. One 
symbol for each IO Bank and a few extras for power and configuration.

Imagine a Bank of IO being used as a memory interface. A number of the 
banks pins are conected to a data bus others are connected to an address 
bus.


GAF symbol libraries.

1) GAF should have a collection of symbol libraries that normally arn't 
modified. The pins stay in the same place in the symbol and the pin 
attributes should remain fixed.

2) When starting a project a new GAF library is created in the project 
directory.

3) For a PLD type device I would create a new top level logical symbol 
for what ever the functionality of the pld is ment to be. This new 
symbol should reside in the project GAF library. I also create lower 
level logical symbols for a major functions that the PLD is going to 
implement (the memory controller for example). Each of these lower level 
logical symbols should be in the project GAF library.

4) As I add the PLD (or any other pin swappable device) sub-symbols (an 
IO bank being a sub symbol) into the schematic for a logical symbol, the 
symbol file from the main GAF libraries should be copied into the 
project GAF library and given a unique name. The unique name allows 
multiple instances of the part to be used in a design and each one 
having its pins rearanged in a unique way.


Pin Swapping

1) highlight or re-color a group of pins which may freely be swapped.

2) If in the netlist file PCB could be told which pins could be freely 
swapped (sellect two pins  and use a menu command which generates a list 
of swapped pins)

3) PCB exports a file with a list of swapped pins and causes a GAF 
utility to be run

4) A GAF utility imports the schematic and the swapped pin file. It 
opens the symbol files (in the project GAF library) for the device whos 
pins were swapped and it exchanges the attributes between two pins which 
have been swapped. Not the position and orientation of the two pins 
remains the same just that their attributes are swapped. Normally these 
atributes would be the pinnumber and pinlabel.

5) PCB upon completion of the pin swapping gaf utility causes gnetlist 
to be run

6) PCB then imports the new netlist



Gate Swapping

Gate swapping can be very similar to pin swapping in that PCB is told 
which devices have multiple gates and what the pins are for each gate. 
PCB then generates a list of swaped gates and exports it to a gaf 
utility which modifies the schematic. PCB then asks that gnetlist be 
run. Then pcb imports the the new netlist.



As I said, just a few wild ideas which would make my life easier.

Steve Meier

P.S. Ales I haven't forgotten your questions. I am just so wrapped up in 
this layout that I havn't taken the time to put my thoughts together. I 
expect the layout done early this week and then I am going to turn some 
of my attention back to the hierarchical bus issue.