Re: gEDA: Problems with connection scanning

[Dan McMahill <dan@mcmahill.net>]

On Sat, Aug 07, 2004 at 08:19:05PM +0000, Karel Kulhav? wrote:
> > 
> > I see C99 which has the broken connection, but I'm having trouble seeing the 
> > tiny stub.  It is visible on the screen for you or only in the .pcb file?
> 
> No it's not visible. Turn the pads off or turn on the transparent mode
> (thin draw).

ok.  I have created a much simplified layout which shows this issue and filed
a bug report on sourceforge.  I won't have time for a few weeks to look into
it so maybe someone else will or at least it won't get totally lost.

> > I think you mean "bypassing" instead of "blocking".
> 
> Yes I have self-learned the elctronics and lack any formal knowledge. What's
> the difference between bypassing and blocking?

"bypassing" is the term used to describe what you have.  A capacitor between
supply pins.  Blocking might be applied to a coupling capacitor since it
blocks the DC voltage between the 2 circuits.  


> First I done the fill with couple of bigger polygons. But then I send the
> board to the manufacture. They refused it because there were tiny triangles
> that were garbage from the polygons when they got clearanced from three sides.
> Sometimes these pieces were thinner than minimum width etc.
> 
> They said these small triangles can peel off, float in the bath and stick
> somewhere else and cause a short-circuit. So I broke the polygons on each
> such a tiny piece and replaced with several smaller polygons that didn't
> cover the area the tiny piece existed.

ah.  I know what you mean.  PCB currently does not perform any
"island removal".  Some commercial tools have a feature where you can specify
a minimum copper area for any polygon.  If after a copper pour, there are any
small isolated area with an area less than the threshold, they are removed.

-Dan

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