Re: gEDA: Problems with connection scanning

[Karel Kulhavý <clock@twibright.com>]

> 
> I see C99 which has the broken connection, but I'm having trouble seeing the 
> tiny stub.  It is visible on the screen for you or only in the .pcb file?

No it's not visible. Turn the pads off or turn on the transparent mode
(thin draw).

> I think you mean "bypassing" instead of "blocking".

Yes I have self-learned the elctronics and lack any formal knowledge. What's
the difference between bypassing and blocking?

> I'm curious, it seems that you have lots and lots of smaller polygons in copper.
> Is there a reason for not just having one large polygon for your VSS/VDD fill?

It's said the polygons should be convex to speed up the operation.

First I done the fill with couple of bigger polygons. But then I send the
board to the manufacture. They refused it because there were tiny triangles
that were garbage from the polygons when they got clearanced from three sides.
Sometimes these pieces were thinner than minimum width etc.

They said these small triangles can peel off, float in the bath and stick
somewhere else and cause a short-circuit. So I broke the polygons on each
such a tiny piece and replaced with several smaller polygons that didn't
cover the area the tiny piece existed.

Then they said the design is OK and that it passes their manufacturing
requirements.

Cl<
> 
> -Dan
> 
> --