Re: gEDA: Problems with connection scanning

[Dan McMahill <dan@mcmahill.net>]

On Sat, Aug 07, 2004 at 02:42:59PM +0000, Karel Kulhav? wrote:
> Hello
> 
> On Ronja project, there happened a real incident with the connection
> scanning algorithm in PCB.
> 
> There was a blocking capacitor C99 ( see
> http://ronja.twibright.com/schematics/twister.pcb.old, coords 2844, 684 ) whose
> pin has been overlapped with a polygon with clearing set to on. And there was
> also a tiny stub of line at the same place.


I see C99 which has the broken connection, but I'm having trouble seeing the 
tiny stub.  It is visible on the screen for you or only in the .pcb file?

> The conenction scanning algorithm thought that the pin and plane are connected,
> presumably due to the existence of the stub and did not generate error. In the
> output, they weren't connected. After removing the stub, the problem has been
> resolved.
> 
> This issue has been spotted by a user after about 550 pieces of the board have
> been manufactured. (It may demonstrate how serious the problem is, or how lousy
> my design quality control on Ronja is, choose yourself ;-) ) It fortunately
> didn't have any impact on the performance of the device because the capacitor
> is blocking and the whole device is sufficiently blocked.

I think you mean "bypassing" instead of "blocking".

> The problem has been caused of course by the designer (me) and not PCB
> software.  However I ask if it would be possible to implement a change into the
> connection scanning algorithm that would prevent such cases, or if there is
> some proven recipe to scan for this type of peciliarities at once at the end of
> the design.

I think this is clearly a bug which needs to be fixed.

I'm curious, it seems that you have lots and lots of smaller polygons in copper.
Is there a reason for not just having one large polygon for your VSS/VDD fill?

-Dan

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