gEDA: Problems with connection scanning

[Karel Kulhavý <clock@twibright.com>]

Hello

On Ronja project, there happened a real incident with the connection
scanning algorithm in PCB.

There was a blocking capacitor C99 ( see
http://ronja.twibright.com/schematics/twister.pcb.old, coords 2844, 684 ) whose
pin has been overlapped with a polygon with clearing set to on. And there was
also a tiny stub of line at the same place.

The conenction scanning algorithm thought that the pin and plane are connected,
presumably due to the existence of the stub and did not generate error. In the
output, they weren't connected. After removing the stub, the problem has been
resolved.

This issue has been spotted by a user after about 550 pieces of the board have
been manufactured. (It may demonstrate how serious the problem is, or how lousy
my design quality control on Ronja is, choose yourself ;-) ) It fortunately
didn't have any impact on the performance of the device because the capacitor
is blocking and the whole device is sufficiently blocked.

The problem has been caused of course by the designer (me) and not PCB
software.  However I ask if it would be possible to implement a change into the
connection scanning algorithm that would prevent such cases, or if there is
some proven recipe to scan for this type of peciliarities at once at the end of
the design.

You can see the PCB source at
http://ronja.twibright.com/schematics/twister.pcb.old
coords 2844, 684

Cl<