Re: gEDA: Hardware accelerated simulation

[Stephen Williams <steve@icarus.com>]

frank_bennett@agilent.com said:
> Assume we could manually partition the design (until another tool
> comes along) by running block_a on a remote processor. On this remote
> processor block_a would require a wrapper, which is a PLI. This remote
>  PLI wrapper would perform a value change dump of output  port changes
> and send the information over a socket connection  which talks to
> "$pli_instance block_a".

Hmmm. Color me skeptical.

However, there are I think PLI tools around the net for connecting
Verilog programs via sockets. From memory, these work by allowing
a Verilog program to create sockets and send/receive messages.

I'm skeptical, however, because I'm not so sure it is practical to
partition a simulation into sufficiently independent parts. One of the
reasons for putting something onto a big chip is that the parts need
to communicate a whole lot.

Using a shared memory multiprocessor (or better yet a cleverly designed
SIMD processor) should provide more benefit, but even at that you need
to keep relatively large chunks of independent devices. At this scale,
though, I bet it would be possible for example to implement a bus in
PLI and bus clients in Verilog, and run each client on a different
processor. That would probably work well. SOC devices seem to have
a bus architecture like that, so this might be a practical way to
accelerate simulations of such designs.

Of course, you can't simulate the *bus* this way:-(

On the other end of the scale, however, the VVP assembly language is
designed to be amenable to hardware implementations.

-- 
Steve Williams                "The woods are lovely, dark and deep.
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