gEDA: strings in iverilog 0.5

[Ales Hvezda <ahvezda@seul.org>]

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Hello, Steve,
I have attached a small test program that exhibits a couple of problems with=
=20
strings which do not occur on verilog-XL.

My view is that there are potentially three problems:
1)  I just want to simulate, not compile into gates.  My guess is that the=20
error "Unable to elaborate ... as gates" should be a Warning that only=20
occurs, if a =B4compile=B4 switch at the command line call is active. =20
2) I am not 100% sure but strings can be assigned also to net types, not onl=
y=20
to reg ??
3) The entire function seems not to elaborate , line 7. =20

What=B4s your view?

J=FCrgen

> iverilog test.v
test.v:8: error: Unable to elaborate `"Mes0"' as gates.
test.v:9: error: Unable to elaborate `"Mes1"' as gates.test.v:10: error:=20
Unable to elaborate `"Mes2"' as gates.test.v:11: error: Unable to elaborate=20
`"Mes3"' as gates.test.v:7: error: Unable to elaborate statement in function=
=20
test.message.test.v:15: error: Unable to elaborate `"hi"' as gates.
test.v:15: error: Unable to elaborate r-value: "hi"test: error: 5 elaboratin=
g=20
module.  =20

module test();
wire [31:0] A;
reg  [31:0] B;

function [31:0] message;
        input [1:0] reg_num;
  begin
        assign message =3D (reg_num =3D=3D 2'b00) ? "Mes0":
                         (reg_num =3D=3D 2'b01) ? "Mes1":
                         (reg_num =3D=3D 2'b10) ? "Mes2":
                                              "Mes3";
  end
endfunction

assign A =3D "hi";
initial=20
  begin
    B =3D "ho";
    #1;
    $display ("%s", A);
    $display ("%s", message(1));
    $finish;
  end
endmodule