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Re: gEDA: Hardware accelerated simulation
[ Ales here, I'm reposting this since majordomo didn't recognize the
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-- Cut here --
Peter Monta <pmonta@halibut.imedia.com> writes:
> I'm wondering how practical it might be to run simulations on
> general-purpose clusters, similar to the Beowulf effort for scientific
> computation.
Peter, Steve:
This old thread is always timely.
Some designs are getting so big that they run slow and consume
all of the available swap space that a distributed verilog
solution would solve.
Assuming a design is hierarchical and mostly structural:
main
test_stimulus
top
top
pads
core
core
$pli_instance block_a
instance block_b
etc.
Assume we could manually partition the design (until
another tool comes along) by running block_a on a
remote processor. On this remote processor block_a
would require a wrapper, which is a PLI. This remote
PLI wrapper would perform a value change dump of output
port changes and send the information over a socket connection
which talks to "$pli_instance block_a". This $pli_instance
would receive changes from the remote and propagate them
inside of the core block. Any changes in the core block
that are connected to block_a would have to be transmitted
back to remote block_a. The PLIs would also have to maintain
"sync" via either a clock or run in time sync. The time sync
information is also part of the vcd format if all the simulations
start at time zero.
Then there would need to be a control function that gets all
the simulations launched, running and opens the one-one socket
connections to each remote.
Or maybe if each block was a seperate threaded process...
which run on seperate processors there might be less work.
Sim-ranches (in colorado, farms elsewhere) are cheap, where
FPGAs are cute but there are no standards and additional tools
are needed. You usually need to retarget the synthesys to
some hardware CLB and not necessairly the gates you really
want. And then turns are not quick (hours to re-
sythesize, map and load) and block is still an issue.
Frank
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