gEDA: Icarus verilog issues/ problems

["Debashis Goswami" <debashis.goswami@wipro.com>]

Hi,

I have successfully installed Icarus verilog 0.5 in Linux (Mandrake 7.2) and
started playing with iverilog. Mostly it is OK, but stumbled on a few cases.
Would you please check the following modules (I attach them at the end of
this mail).

module hello: Icarus verilog does not display anything, but verilog-xl
displays hello world thrice (problem with implicit wire?)
module for_test: Icarus verilog gives abort message (may be 'for' not
supported yet?)

-Debashis

----------------------------------------------------------------------------
-----------
module hello;

reg clkr;

temp U_temp(clk);

assign clk = clkr;

initial begin
 clkr = 0;
 #500 $finish;
end

task disp_hello;
input   [2:0]   sno;
begin
        @(negedge clk)
 $display("%d: hello world", sno);
end
endtask

initial begin
 disp_hello(3'b000);
 disp_hello(3'b001);
 disp_hello(3'b010);
end

always #25 clkr = ~clk;

endmodule

module temp(clk);
input clk;
endmodule
----------------------------------------------------------------------------
------------

`define SIZE 15

module for_test ( a, b, co );

input [`SIZE:0] a, b;
output co;

reg [`SIZE:0] co_reg;
reg co;
integer i;

always @ (a or b or co_reg)
begin
        for ( i = 0; i <= `SIZE; i = i + 1)
                co_reg[i] = a[i] | b[i];

 co = |co_reg;
end

endmodule

----------------------------------------------------------------------------
-------------


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