Re: gEDA: iverilog/tgt-edif update

[volodya@mindspring.com]

On Sun, 5 Aug 2001, Stephen Williams wrote:

> 
> volodya@mindspring.com said:
> >       - produces output that edif2ngd.exe does not
> >         complain about (I don't have the hardware to 
> >         further test it) 
> 
> You don't need hardware. Use fpgaedit to see what the PPR does
> with it.

I don't have it. I am using WebPACK ISE - would you know of a proper
command from it ? I have not been able to get Project Navigator 
(that fancy GUI that comes with it) to recognize that I want to process my
own edif netlist and not theirs. Oh well - this is pretty much academic
exercise anyway as I don't know of any open source Xilinx P&R tool, so
I'll have to use Windows at some point. I just wanted to study the
differences in EDIF syntax between two manufacturers to get an idea in
which direction to generalize. 

Btw, what is in your opinion the right way to tell the netlister that
certain parts of code should use chained adders and some other parts
should use fast adders ?

                         Vladimir Dergachev

> -- 
> Steve Williams                "The woods are lovely, dark and deep.
> steve@icarus.com              But I have promises to keep,
> steve@picturel.com            and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> 
>